For complying with the increasing processing frequency of a core of a computer system chip, data transmitted via I/O buses are preferably parallel data. However, problems are likely to occur during the transmission of parallel data signals. For example, power/ground bounce noise is likely generated at the input and output ends. Generally, when the output end of an output buffer is in switching status, a power/ground bounce noise is derived from the flow of intense current through the parasitic inductance of the bonding wires, lead frame or pin. In addition, it may suffer from a so-called SSO (simultaneous switching output) skew phenomenon.
Please refer to FIG. 1, which schematically illustrates conventional output buffers commonly electrically connected to a power voltage and a ground voltage. Each of the output buffers B1˜Bn is coupled to both of a common power source Vpp and a common ground Vss. Since the common power source Vpp is electrically connected to a pad via pins and bounding wires, parasitic inductances associated with the pins and pad/bounding wires will be generated between the output buffers B1˜Bn and the common power source Vpp, which is indicated by an equivalent inductance L1. Likewise, pin parasitic inductance and pad/bounding-wire inductance are generated between the output buffers B1˜Bn and the common ground Vss, which is indicated by an equivalent inductance L2.
Due to the existence of the parasitic inductances L1 and L2 between the output buffers B1˜Bn and the common power source and ground Vpp and Vss, respectively, when some of the output buffers B1˜Bn change their output states at the same time, instaneous current change will result in the undesirable power/ground bounce effect.
Please refer to FIG. 2. When a number of output buffers simultaneously change their output states from a low level to a high level, the SSO skew phenomenon is likely to occur so as to delay the parallel data signal MD to some extent, as indicated by a period T1 of FIG. 2. Likewise, for the change of the output states of the output buffers from a high level to a low level, the parallel data signal MD is delayed as indicated by a period T2 of FIG. 2 due to the SSO skew phenomenon. The degree of the SSO skew is dependent on numbers of output buffers on changing. That is to say, when more output buffers change from the low level to the high level or the high level to the low level at the same time, the SSO skew becomes more serious, and the delayed period T1 or T2 is increased.
Along with the parallel data signal, a strobe signal DQS is outputted to decide when a downstream device should pick up the parallel data. Generally, the rising and falling edges of the strobe signal DQS are located within effective access ranges of the parallel data signal MD and preferably in the middle of the effective access ranges. Due to the SSO skew, the time margin allowing the downstream device to pick up the parallel data in response to the original strobe signal is even limited if a large quantity of parallel data required to be processed by the I/O bus. For example, parallel data of up to 64 bits are simultaneously processed by a Dynamic Random Access Memory (DRAM) or a central processing unit (CPU). The reduced time margin leads to the difficulty in receiving data or obtaining accurate data.